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p reliminary w91030b calling line identif ier publication release date: m ar ch 2000 - 1 - revision a1 table of contents - general description ................................ ................................ ................................ .............................. 2 features ................................ ................................ ................................ ................................ ...................... 2 pin configuration ................................ ................................ ................................ ................................ .... 3 pin description ................................ ................................ ................................ ................................ .......... 3 system diagram ................................ ................................ ................................ ................................ ........ 5 block diagram ................................ ................................ ................................ ................................ ........... 5 functional description ................................ ................................ ................................ ........................ 6 ring detector ................................ ................................ ................................ ................................ ................. 6 input pre - processor ................................ ................................ ................................ ................................ ....... 7 dual tone alert signal detection ................................ ................................ ................................ .................... 7 fsk demodulation ................................ ................................ ................................ ................................ ......... 9 other functions ................................ ................................ ................................ ................................ ........... 11 electrical characteristics ................................ ................................ ................................ .............. 13 abso lute maximum ratings ................................ ................................ ................................ ......................... 13 recommended operating conditions ................................ ................................ ................................ ........... 13 dc electrical characteristics ................................ ................................ ................................ ........................ 13 electrical characteristics - gain control op - amplifier ................................ ................................ .................. 15 ac electrical characteristics ................................ ................................ ................................ ........................ 15 ac timing characteristics ................................ ................................ ................................ ........................... 16 application information ................................ ................................ ................................ ..................... 21 application circuit ................................ ................................ ................................ ................................ ........ 21 application environment ................................ ................................ ................................ .............................. 23 package dimensions ................................ ................................ ................................ .............................. 29 the information described in this document is the exclusive intellectual property of winbond electronics corporation and shall not be reproduced without permi ssion from winbond. winbond provides this document for reference purposes of w - based system design only. winbond assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice.
p reliminar y w91030b - 2 - general description the w inbond caller identification device w91030b, is a low power cmos integrated circuit used to receive physical layer signals transmitted according to bellcore and british telecom (bt) specifications. there are two types of caller identifications, the first t ype is on - hook calling with caller id message and the second type is call on waiting. the w91030b device provides all the features and functions of the caller identification specification for both these types, including fsk demodulation, tone alert signal detection and ring detection. the fsk demodulation function can demodulate bell 202 and ccitt v.23 frequency shift keying (fsk) with 1200 baud rate. the tone alert signal detect function can detect the dual tones of the bellcore cpe* tone alerting signal ( cas) and the bt idle state and loop state tone alert signal. the line reversal for bt, ring burst for cca or ring signal for bellcore can be detected by the ring detector. there are two modes of fsk data output interface. the first mode is a data transfer activated by the device, whose clock and data change depending upon the changing frequency of the fsk analog signal input. the second mode allows a microcontroller to extract 8 - bit data from the device serially; the device notifies the micro - controller whe n 8 - bit data has been received. note: "cpe*" customer primises equipment features compatible with bellcore tr - nwt - 000030 & sr - tsv - 002476, british telecom (bt) sin227, u.k. cable communications association (cca) specification ring and line reversal de tection bellcore cpe alerting signal (cas) and bt idle state and loop state tone alerting signal detection use dual tone alerting signal detector bell 202 and ccitt v.23 fsk demodulation with 1200 baud rate use 3.579545 mhz crystal or ceramic resona tor low power cmos technology with sleep mode high input sensitivity variable gain input amplifier fsk carry detect output two modes for 3 - wire fsk data interface packaged in 24 - pin 0.6 inch (600 mil) plastic dip (w91030b) and 24 - pin 0.3 inch ( 300 mil) plastic sop (w91030bs). applications bellcore calling identity delivery (cid), and bt calling line identity presentation (clip), cca clip systems feature phones phone set adjunct boxes fax and answering machines data base telephone syst em and computer telephony integration (cti) systems
p reliminary w91030b publication release date: march 2000 - 3 - revision a1 pin configuration v algrc algr algo intn fcdn fdrn data dclk fske sleep/reset test2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 inp inn gcfb vref cap rngdi rngrc rngon mode osci osco v top view dd ss pin description pin name type description 1 inp i non - inverting input of the gain control op - amp. 2 inn i inverting input of the gain control op - amp. 3 gcfb o op - amp feed - back gain control signal. select the input gain by connecting this pin and the inn pin with a feed - back resistor. it is recommended that the op - amp be set to unity gain. 4 vref o reference voltage. nominally, v dd /2 is used to bias the input of t he gain control op - amp. 5 cap o must be connected a 0.1 m f capacitor to v ss . 6 rngdi i ring detect input (schmitt trigger input). used for ring detection and line reversal detection. must maintain a voltage between v dd and v ss . 7 rngrc o ring rc (open d rain output and schmitt trigger input). used to set the time interval from the end of rngdi pin to the inactive condition of the rngon pin. an external resistor must connected to v dd and a capacitor connected to v ss , the time interval is the rc time consta nt. 8 rngon o ring detection output (low active). indicates the detection of line reversal and/or ringing. 9 mode i fsk data interface mode select. sets the fsk data output interface in mode 0 when low, or in mode 1 when high. 10 osci i oscillator input . a 3.579545 mhz crystal or ceramic resonator should be connected between this pin and the osco pin. may be driven by an external clock source.
p reliminar y w91030b - 4 - pin descriptions, continued pin name type description 11 osco o oscillator output. a 3.579545 mhz crystal or ceramic resonator should be connected between this pin and the osci pin. should left open or to drive another clocked device when an external clock is connected to the osci pin. 12 v ss i power supply ground. 13 test i test pin. must be connected to v ss for normal operation. 14 sleep/ reset i reset or sleep input (schmitt input). when high the device will be reseted and enter a low power state by disabling the gain control op - amp, the oscillator and other internal circuits. the function of rngdi, rngrc a nd the rngon pins are not affected when the device is in a sleep condition. this pin must be set low for normal operation. the device must reseted by micro controller or by external rc pulse after power on. 15 fske i fsk enable. must be set high when for fsk demodulation. may be set low to disable the fsk demodulator when fsk signal is not expected. 16 dclk i, o data clock for the fsk interface. in the fsk data output interface mode 0 (mode pin low), this pin is an output with a changing fsk frequency. in the fsk interface mode 1, this pin is an input. 17 data o data signal for the fsk interface. serial data output according to the fsk frequency input in fsk data output interface mode 0 (mode pin low). data is shifted out on the rising edge of dclk in fsk data output interface mode 1. both logic 1 for mark and logic 0 for space. 18 fdrn o data ready of the fsk interface (low active). in fsk interface mode 0 (mode pin low), this pin identifies the 8 - bit data boundary on the serial output string. in fsk int erface mode 1, this pin is used to notify the micro - controller to extract the 8 - bit data (ie. 8 - bit data has been ready internally). 19 fcdn o fsk carrier detect (low active). when low, it indicates the fsk signal has been detected. 20 intn o interrupt s ignal (open drain). it is used to interrupt the microcontroller when rngon or fdrn are low, or if algo is high. remains low until all three signals have become inactive. 21 algo o dual tone alert signal guard time detect output. when high, a guard time qu alified for the dual tone alert signal has been detected. 22 algr o dual tone alert signal guard time resistor. also functions as a dual tone alert signal detect output without guard time. an external resistor must connected between this pin and algrc to implement guard time detection. 23 algrc i dual tone alert signal guard time rc (cmos output and internal voltage comparator input). an external resistor must be connected between this pin and algr and an external capacitor between this pin and v dd to imp lement guard time detection. 24 v dd i power supply input.
p reliminary w91030b publication release date: march 2000 - 5 - revision a1 system diagram the w91030b device applications include telephone systems which have caller id features and which can display the calling message on an lcd display. figure 5 shows the system diag ram. it illustrates how to use the chip to connect between the tip/ring and the microcontroller in the telephone system. the ring signal is detected by the w91030b device and then an interrupt sent to the microcontroller. the ring detected signal will also be directed to the ringer circuit. the data can be decoded by the microcontroller and displayed on the lcd display. the dtmf ack signal can also be generated by the dtmf generator if a call on waiting is performed. other functions are the same as the tel ephone set. figure 5. system diagram for caller id application block diagram inp inn + - anti-alias filter fsk bandpass filter fsk demodulator fsk data output interface fsk carrier detector high tone bandpass filter low tone bandpass filter guard time circuit bias voltage generator to internal circuit oscillator & clock driver to internal circuit vref algo algrc intn fcdn fdrn data dclk sleep/ reset osci osco rngdi rngrc rngon vdd vss gcfb fske mode algr input pre-processor fsk demodulation circuit dual tone alert signal detection circuit ring detector high tone detector low tone detector interrupt generator power down control power down control cap figure 6. the block diagram of w91030b micro controller handset speaker line interface winbond caller id ( w91030b ) dtmf generator keypads lcd display ringer tip ring
p reliminar y w91030b - 6 - functional descripti on figure 6 is shown functional blocks of w91030b . the device must operate with a 3.579545 mhz system clock and consists four major functions and decribed as follows: ring detector the application circuit in figure 7 - 1 illustrates the relationship between the rngdi, rngrc and rngon signals. the three pin combination is used to detect an increase of the rngdi voltage from ground to a level above the schmitt trigger high going threshold voltage v t+ . figure 7 - 1. application circuit of the ring detecter the rc time constant of the rngrc pin is used to delay the output pulse of the rngon pin for a low going edge on rngdi. this edge goes from above the v t+ voltage to the sch mitt trigger low going threshold voltage v t - . the rc time constant must be greater than the maximum period of the ring signal, to ensure a minimum rngon low interval and to filter the ring signal to get an envelope output. tip/a r1 = 470k c1 = 0.1uf ring/b c1 = 0.1 uf c3 = 0.22 uf r5 = 150 k r2 = 470 k r3 = 200 k r4 = 300 k rngdi w91030b rngrc rngon allowanc e minimal ring voltage (peak to peak) is: vpp ( max ring) = 2 ( v t+(max) (r1 + r3 + r4) / r4 + 0.7) tolerance to noise between tip and ring and vss is: vpeak ( max noise) = v t+(min) (r1 + r3 + r4) / r4 + 0.7 time constant is: t = r5 c3 ln [v / (v - v t+ )] v t+(min) <= v t+ <= v t+(max) r5 from 10k ohm to 500k ohm. c3 from 47 nf to 0.68 uf. dd dd v dd v dd
p reliminary w91030b publication release date: march 2000 - 7 - revision a1 the diode bridge shown in figure 7 - 1 works for both single ended ring signal and balanced ringing. r1 and r2 are used to set the maximum loading and must be of equal value to achieve balanced loading at both the tip and ring line. r1, r3 and r4 form a resistor divider to supply a reduced voltage to the rngdi input. the attenuation value is determined by the detection of minimal ring voltage and maximum noise tolerance between tip/ring and ground. input pre - processor the input signal is processed by an input pre - processor, which is added t o the offset voltage to adjust the input amplitude and to filter out unwanted frequencies. the gain control op - amp is used to bias the input voltage with the vref signal voltage. the voltage of vref pin is v dd /2 typically, this pin had better connected a 0 .1uf capacitor to v ss . it is also used to select the input gain by connecting a feedback resistor between this pin and the inn pin. figure 7 - 2 shows the necessary connections with the tip/ring line inputs. in a single - ended configuration, the gain control op - amp is connected as shown in figure 7 - 3. figure 7 - 2 differential input gain control circuit figure 7 - 3 single - ended input gain control circ uit dual tone alert signal detection the dual tone alert signal is separated into high and low tones and detected by a high/low tone detector. the dual tone alert signal detection circuit is always enabled when the w91030b/bs is not in sleep state. the a lgr is the output of the dual tone detector and when high indicates that the high tone and low tone alert signals have been detected. the guard time improves detection performance by rejecting detected signals with insufficient duration and by masking mome ntary detection dropout. figure 7 - 4 shows the relationship between the algr, algrc and algo pins and figure 7 - 5 shows the guard time waveform of the same pins. the total recognition time is t rec = t dp + t gp , where t dp is the tone present detect time and t g p is the tone present guard time. the tone present guard time is the rc time constant with the capacitor discharging from v ss to v dd ( the algrc pin discharges from v ss to v dd through a resistor). the capacitor will discharge rapidly via a discharge switch after algo returns high. the total absent time is t abs = t da + t ga , where t da is the tone absent detect time and t ga is the tone absent guard time. the tone absent guard time is the rc time constant with the inp inn + - gcfb r1 c1 c2 r2 r4 r3 r5 vref tip ring w91030b differential input amplifier c1 = c2 r1 = r2 r3 = (r4 r5) / (r4 +r5) voltage gain av = r5 / r1 input impedance zin = 2 r1 2 + (1 / wc) 2 0.1 uf c r1 r2 input + - inp inn gcfb vref voltage gain v a = r2 / r1 w91030b 0.1 uf
p reliminar y w91030b - 8 - capacitor charging from v dd to v ss (the algrc p in charges from v dd to v ss through a resistor). the capacitor will charge rapidly via a charge switch after algo returns low. to obtain unequal present and absent guard times, a diode can be connected as shown in figure 7 - 6, to give the unequal resistance required during capacitor charging and discharging. figure 7 - 4. guard time circuit of dual tone alert signal detection algr algrc algo discharge switch charge switch tip/ring on on on alerting signal v cpth v cpth t dp t gp t rec t da t ga t abs figure 7 - 5. guard time waveform of algr, algrc and algo pins dual tone detected v cpth - + comparator w91030b algrc algr algo vdd vdd r c dischar ge switch charge switch capacitor charge/discharge control circuit
p reliminary w91030b publication release date: march 2000 - 9 - revision a1 figure 7 - 6. guard time circuits with unequal present and absent time fsk demodulation the fsk demodulation circuit is enabled when the fske signal is high. an enable time i s required to enable the fsk demodulator circuitry after the fske signal goes from low to high. fsk carrier detector the fsk carrier detector provides an indication of the presence of a signal within the fsk frequency band. if the output amplitude of the f sk bandpass filter is of sufficient magnitude and holds for 8 ms, the fsk carrier detect output signal fcdn goes low. fcdn will be released if the fsk bandpass filter output amplitude is of insufficient magnitude for greater than 8 ms. the 8 ms hysteresis of the fsk carrier detector is to allow for momentary signal drop out after fcdn has been activated. when fcdn is inactive, the output of the fsk demodulator is ignored by the fsk data output interface. in mode 0 of the 3 - wire fsk data output interface, dc lk data and fdrn are all high and no clock and no data is driven. in mode 1, the internal shift registers are not updated, and fdrn is inactive (high state). the data is undefined if dclk is clocked. 3 - wire fsk interface the 3 - wire interface, dclk, data an d fdrn pins, form the data interface of the fsk demodulation. the dclk pin is the data clock which is either generated by the w91030b or by an external device. the data pin is the serial data pin that outputs data to external devices. the fdrn pin is the d ata ready signal, also an output from the w91030b to external devices. there are two modes of this 3 - wire interface that can be selected. mode 0, where the data transfer is initiated by the w91030b device, or mode 1, where the data transfer is initiated by an external microcontroller. ( a) t gp > t ga t gp dd = r1 c ln [v dd cpth / ( v - v )] t g a = r p c ln [(v dd - v d ( r p / r2)) / (v cpth - v d ( r p / r2))] r p = r1 r2 / (r1 + r2) v d = diode forward voltage r1 r2 c algrc alr w91030b r1 r2 c algrc alr w91030b ( b) t gp > t ga t gp dd = r1 c ln [v dd cpth / ( v - v )] t ga = r p c ln [(v dd - v d ( r p / r2)) / (v - v cpth - v d ( r p / r2))] r p = r1 r2 / (r1 + r2) v d = diode forward voltage dd v dd v dd
p reliminar y w91030b - 10 - mode 0 (mode = low): the w91030b processes the fsk signal and outputs signals on the dclk, data and fdrn pins. figure 7 - 7 shows the timing diagram of the 3 - wire signals and the input of the fsk signal in mode 0. for each rec eived stop and start bit sequence, the device outputs a fixed frequency clock string of 8 pulses on the dclk pin. each clock rising edge occurs in the middle of each data bit. dclk is not generated for the stop and start bits. the dclk pin is used as a clo ck driving signal for a serial to parallel shift register or for a serial data input for a microcontroller. after the 8 - bit data has been shifted out by the device, the fdrn pin will supply a low pulse to inform the microcontroller to process the 8 - bit da ta. tip/ring 1* 1 0 b0 b1 b2 start b3 b4 b5 b6 b7 1* 0 b0 b1 b2 b3 b4 b5 b6 b7 1 1 0 b0 stop start stop start data b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 start stop start stop start t idd dclk fdrn 1/f dclk0 t crd t rl 1st byte data 2nd byte data 1st byte data 2nd byte data * mark bit or redundant stop bit(s), will be omitted. figure 7 - 7. serial data interface timing of fsk demodulation in mode 0 mode 1 (mode = high): the w91030b processes the fsk signal and sets the fdrn pin low to denote the 8 - bit boundary and to indicate to the microcontroller that new data has been transmitted. fdrn will return high on the first rising edge of dclk. fdrn is low for half of a nominal bit time (1/2400 sec) if dclk is not driven high. dclk is used to shift 8 - bit data out (lsb shift first) on the rising edge. after the last bit (msb) has been read, additional clock pulses on dclk are ignored. figure 7 - 8 shows the timing diagram of the 3 - wire signals and the input of the fsk signal in mode 1.
p reliminary w91030b publication release date: march 2000 - 11 - revision a1 demodulated internal bit stream start 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 stop stop start data b0 b1 b2 b3 b4 b5 b6 b7 dclk fdrn 1/f dclk1 b7 b6 b5 1 b0 b0 b7 b6 t dds t ddh nth byte data (n + 1)th byte data (n - 1)th byte data nth byte data t rl note 2 note 1 1. fdrn cleared to high by dclk. 2. fdrn not cleared, low for maximum time (1/2 bit width). notes: figure 7 - 8. serial data interface timing of fsk demodula tion in mode 1 other functions interrupt the interrupt intn is an open drain output and is used to interrupt the microcontroller. either rngon low, fdrn low or algo high will set intn low and will remain low until all of these three pins return to an inact ive state. the microcontroller must read these pins to know what kind of interrupt occurred and to make the correct interrupt response. when the system is powered on, there is no charge on the capacitors. the voltage on the rngrc pin is low and rngon will be low. also the voltage on the algrc pin is high and algo will be high if the sleep pin is low. this will cause an interrupt upon power up which will not be cleared until both capacitors are charged. the microcontroller should therefore ignore the interru pt from these source until the capacitors are charged up. the microcontroller can examine the rngon and algo pins and wait until these signals are inactive during a power on interrupt. it is possible to clear the algo pin and its interrupt quickly by setti ng the sleep pin high. in the sleep mode, the algo pin is forced low and the charge switch in figure 7 - 4 will turn on, forcing the capacitor to charge up rapidly. sleep mode the w91030b can go into a sleep mode by setting sleep high, resulting in reduced p ower consumption. in this mode, the gain control op - amp, oscillator and all internal circuits, except the ring detector are disabled. the rngdi, rngrc and rngon pins are not affected, so the device can still react to call arrival indicators and activate an interrupt to wake up the microcontroller. the sleep mode can be disabled by the microcontroller.
p reliminar y w91030b - 12 - crystal oscillator the operation frequency of the w91030b is 3.579545 mhz. crystal oscillators, ceramic resonators or other clock sources can be used. a crys tal oscillator or ceramic resonator can be directly connected to the osci and osco pins without the need for external components. if other clock sources are used, the osci pin should be driven by a clock source and the osco pin used to drive other external clocked devices, or left open. figure 7 - 9 shows some applications. the crystal specification is as follows: frequency: 3.579545 mhz frequency tolerance: +/ - 0.1 % ( - 40 c to +85 c) resonance mode: parallel load capacitance: 18 pf maximum series resis tance: 150 w maximum drive level (mv): 2 mv figure 7 - 9. some application of clock driven circuit bias voltage generator the bias voltage generator provides a low impedance voltage source equal to v dd /2 and i s used to bias the gain control op - amp. the voltage source is also used for internal circuits. a 0.1 m f capacitor had better be placed between the vref pin and v ss to reduce noise. (a) with crystal o sscillator or ceramic resonator (b) with other clock source osci osco 3.579545 mhz oscillator osco osci osco osci osco w91030b w91030b w91030b osci osco 3.579545 mhz w91030b
p reliminary w91030b publication release date: march 2000 - 13 - revision a1 electrical character istics absolute maximum ratings (voltage referenced t o v ss pin) parameter symbol rating units supply voltage with respect to v ss v dd - 0.3 to 6 v voltage on any pin other than supplies (note 1) - 0.7 to v dd + 0.7 v current on any pin other than supplies 0 to 10 ma storage temperature t st - 65 to 150 c n otes: 1. v dd +0.7 should not exceed the maximum rating of the supply voltage. 2. exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. recommended operating conditions (volt ages referenced to v ss ) parameter symbol rating unit power supplies v dd 3.0 to 5.5 v clock frequency f osc 3.579545 mhz clock frequency tolerance d f c - 0.1 to +0.1 % operational temperature t op 0 to 75 c dc electrical characteristics (v dd - v ss = 3.0v. the dc electrical characteristics supersede the recommended operating conditions unless otherwise stated.) parameter condition sym. min. typ max. units test/ notes operating supply voltage 3.0 5.0 standby supply current i ddq 1 m a test 1 v dd = 3.0v fske = high i dd1 2.6 3.7 ma test 2 operating supply current v dd = 3.0v fske = low i dd2 1.6 2.3 v dd = 5.0v fske = high i dd1 4.1 5.9 ma v dd = 5.0v fske = low i dd2 2.5 3.6
p reliminar y w91030b - 14 - dc electrical characteristics, continued parameter condition sym. min. typ max. units test/ notes schmitt input high threshold schmitt input low threshold rngdi, rngrc sleep v t+ v t - 0.48 v dd 0.28 v dd 0.68 v dd 0.48 v dd v v schmitt hysteresis v hys 0.2 v cmos input high voltage cmos input low voltage dclk, mode, fske v ih v il 0.7 v dd v ss v dd 0.3 v dd v output high source current rgnon, dclk, data, fdrn, fcdn, algo, algrc, algr i oh 0.5 ma note 1 output low sink current rgnon, dclk, data, fdrn, fcdn, algo, algrc, algr, intn i ol 0.5 ma note 2 rngrc i ol 2.5 ma note 2 input current 1 inp, inn, rngdi i in 1 1 m a note 3, 5 input current 2 sleep, dclk, mode, fske i in 2 10 m a note 3, 5 output high - z current 1 rngrc i oz 1 1 m a note output high - z current 2 algrc i oz 2 5 m a 4, 5 output high - z current 3 intn i oz 3 10 m a reference output voltage vref v r ef 0.5 v dd - 4% 0.5 v dd +4% v note 6 reference output resistance vref r ref 2 k w comparator threshold voltage algrc v cpth 0.5 v dd - 4% 0.5 v dd +4% v tests: 1: all input pins are v dd or v ss except for os cillator pins, no analog inputs, output unloaded and sleep = v dd . 2: all input pins are v dd or v ss except for oscillator pins, no analog inputs, output unloaded, sleep = v ss and fske = v dd or fske = v ss . notes: " " typical figure are at v dd = 5v and tempe rature = 25 c are design aids only, not guaranteed and not subject to production testing. 1. v oh = 0.9 v dd . 2. v ol = 0.1 v dd . 3. v in = v dd to v ss . 4. v out = v dd to v ss . 5. magnitude measurement, ignore signs. 6. output - no load.
p reliminary w91030b publication release date: march 2000 - 15 - revision a1 electrical characterist ics - gain control op - amplifier (electrical characteristics supersede the recommended operating conditions unless otherwise stated.) parameter sym. min. typ . max. units test conditions input leakage current i in 1 ua v ss v in v dd input resistance r in 10 m w input offset voltage v os 25 mv power supply rejection ratio psrr 40 db 1 khz 0.1 vpp ripple on v dd maximum capacitive load (gcfb) c l 100 pf maximum resistive load (gcfb) r l 50 k w note: " " typical figure are at v dd = 5v and temper ature = 25 c are design aids only, not guaranteed and not subject to production testing. ac electrical characteristics (ac electrical characteristics supersede the recommended operating conditions unless otherwise stated.) dual tone alert signal dete ction parameter sym. min. typ . max. units notes low tone frequency f l 2130 hz high tone frequency f h 2750 hz frequency deviation acceptance 1.1 % 1 frequency deviation rejection 3.5 % 2 maximum input signal level 0.22 dbm a 3 input sensi tivity per tone - 37 - 38 dbm 3, 4 reject signal level per tone - 45 - 44 dbm 3, 4 positive and negative twist b accept 7 db noise tolerance snr tone 20 db 3, 4, 5 notes: a. dbm = decibels with a reference power of 1 mw into 600 ohms, 0 dbm = 0.774 6 vrms. b. twist = 20 log (f h amplitude / f l amplitude). 1: the range within which tones are accepted. 2: the range outside of which tones are rejected. 3: these characteristics are for v dd = 5v and temperature = 25 c. 4: both tones have the same amplitud e. both tones are at the nominal frequencies. 5: band limited random noise 300 - 3400 hz. present only when the tone is present.
p reliminar y w91030b - 16 - fsk detection parameter symbol min. typ. max. units notes input frequency detection bell 202 mark (logic 1) bell 202 space (log ic 0) ccitt v.23 mark (logic 1) ccitt v.23 space (logic 0) f mark f space f mark f space 1188 2178 1280.5 2068.5 1200 2200 1300 2100 1212 2222 1319.5 2131.5 hz +/ - 1% +/ - 1% +/ - 1.5% +/ - 1.5% maximum input signal level - 5.78 dbm input sensitivity - 43 - 45 dbm 1, 2 transmission rate 1188 1200 1212 baud input noise tolerance snr fsk 20 db 1, 2, 3 notes: 1. both mark and space have the same amplitude and are at the nominal frequencies. 2. these characteristics are fort v dd = 5v and temperature = 25 c. 3. band limited random noise 300 - 3400 hz. present only when the fsk signal is present. ac timing characteristics (ac timing characteristics supersede the recommended operating conditions unless otherwise stated.) system parameter symbol condition min . typ . max. units notes wake - up time t wake sleep 50 ms sleep - down time t slp osco 1 ms note: " " typical figures are for v dd = 5v and temperature = 25 c are design aids only, not guaranteed and not subject to production testing. dual tone aler t signal detection parameter symbol condition min. typ . max. units notes alert signal present detect time t dp algr 0.5 10 ms alert signal absent detect time t da 0.1 8 ms note: " " typical figure are at v dd = 5v and temperature = 25 c are design a ids only, not guaranteed and not subject to production testing. fsk detection parameter symbol condition min. typ . max. units notes fsk detection enable time t fske fske (high) 25 ms input fsk to fcdn low delay t cp 25 ms
p reliminary w91030b publication release date: march 2000 - 17 - revision a1 fsk detection, contin ued parameter symbol condition min. typ . max. units notes input fsk to fcdn high delay t ca fcdn 8 ms hysteresis 8 ms note: " " typical figure are at v dd = 5v and temperature = 25 c are design aids only, not guaranteed and not subject to pro duction testing. 3 - wire interface (mode 0) parameter symbol condition min. typ . max. units notes rise time t rr 200 ns 4 fall time t rf fdrn 200 ns 4 low time t rl 415 416 417 m s 2 rate data 1188 1200 1212 bps 1 input fsk to data delay t idd 1 5 ms rise time t r 200 ns 4 fall time t f dclk 200 ns 4 data to dclk delay t dcd data 6 416 m s 1, 2, 3 dclk to data delay t cdd 6 416 m s 1, 2, 3 frequency f dclk0 1201.6 1202.8 1204 hz 2 high time t ch dclk 415 416 417 m s 2 low time t cl 415 416 4 17 m s 2 dclk to fdrn delay t crd dclk, fdrn 415 416 417 m s 2 notes: " " ttypical figure are for v dd = 5v and temperature = 25 c, are design aids only, not guaranteed and not subject to production testing. 1. fsk input data rate at 1200 +/ - 12 baud. 2. osci frequency at 3.579545 mhz +/ - 0.1%. 3. function of signal condition. 4. 50 pf loading. 3 - wire interface (mode 1) parameter symbol condition min. typ . max. units notes frequency f dclk1 1 mhz duty cycle dclk 30 70 % rise time t r1 20 ns dcl k low set - up to fdrn t dds dclk, 500 ns dclk low hold time after fdrn t ddh fdrn 500 ns note: " " typical figure are at v dd = 5v and temperature = 25 c are design aids only, not guaranteed and not subject to production testing.
p reliminar y w91030b - 18 - sleep osco t wake t slp figure 8 - 1. wake up and sleep down timing tip/ring algr alerting signal t dp t da alerting signal t dp t da figure 8 - 2. alert signal present and absent detect timing tip/ring fcdn analog fsk signal t cp t ca fske t fske analog fsk signal t cp t ca note figure 8 - 3. fsk detection enable and fsk carrier detect present and absent timing note: the minimal delay f rom fske high to fcdn high is t fske + t cp , if the analog fsk signal is present before t fske has elapsed. data dclk v hm v ct v lm v hm v ct v lm t cl t ch t r t f t dcd t cdd t r t f v hm = 0.7 v , v ct = 0.5 v , v lm = 0.3 v dd dd dd figure 8 - 4. data and dclk mode 0 ouput timing
p reliminary w91030b publication release date: march 2000 - 19 - revision a1 fdrn t rf t rr t rl v hm v ct v lm v hm = 0.7 v , v ct = 0.5 v , v lm = 0.3 v dd dd dd figure 8 - 5. fdrn output timing tip/ring 1* 1 0 b0 b1 b2 start b3 b4 b5 b6 b7 1* 0 b0 b1 b2 b3 b4 b5 b6 b7 1 1 0 b0 stop start stop start data b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 start stop start stop start t idd dclk fdrn 1/f dclk0 t crd t rl 1st byte data 1st byte data 2nd byte data 2nd byte data * mark bit or redundant stop bit(s), will be omitted. figur e 8 - 6. serial data interface timing of fsk demodulation in mode 0 dclk t r1 v hm v lm v hm = 0.7 v , v dd lm = 0.3 v dd figure 8 - 7. dclk mode 1 input timing
p reliminar y w91030b - 20 - demodulated internal bit stream start 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 stop stop start data b0 b1 b2 b3 b4 b5 b6 b7 dclk fdrn 1/f dclk1 b7 b6 b5 1 b0 b0 b7 b6 t dds t ddh nth byte data (n + 1)th byte data (n - 1)th byte data nth byte data t rl note 2 note 1 1. fdrn cleared to high by dclk. 2. fdrn not cleared, low for maximum time (1/2 bit width). notes: figure 8 - 8. serial data interface timing of fsk demodulation in mode 1
p reliminary w91030b publication release date: march 2000 - 21 - revision a1 application informat ion application ci rcuit analog interface the application circuit of the w91030b in figure 9 - 1 shows the device being used within a typical cpe system. note that only the circuit between the w91030b and the line interface is shown. the gain control op - amp is set to unity gai n to allow the electrical characteristics to be met in this application circuit. it should also be noted that if a glitch with sufficient amplitude appears on the tip and ring interface, this will be detected as a ringing input by this circuit. f igure 9 - 1 application circuit another application circuit for the w91030b, which provides common mode rejection of ringing circuit signals, is shown in figure 9 - 2. when the ac voltage between the tip and ring is greater than the zener diode breakdown volt age, the photo - coupler led will turn on, driving rngdi high and thus detecting a ringing signal. note however in this case, a glitch on the tip and ring interface is not able to turn on the photo - coupler and therefore will not be detected as a ringing sign al. inp inn gcfb vref cap rngdi rngon mode osci osco vss rngrc vdd algrc algr algo intn fcdn fdrn data dclk fske sleep/ reset test +5 v 34 k 430 k 22 nf tip/a +5 v 430 k 22 nf ring/b 34 k 464 k 60 k4 +5 v 150 k 0.22 uf 200 k 300 k 0.1 uf +5 v +5 v 0.1 uf r2 r1 +5 v 53 k6 w91030b fsk 3 - wire interface mode 0 selected. resistor must have 1% tolerance. resistor may have 5% tolerance. cry stal is 3.579545mhz with 0.1% frequency tolerance. 470 k 470 k 0.1 uf 10 k +5 v r1, r2 must calculated according to the formula of fig. 7 - 6 (a) for bellcore or bt application. 0.1 uf must rest by microcontroller or by rc pulse. (this net must as short as possible)
p reliminar y w91030b - 22 - application information, continued figure 9 - 2. application circuit with improved common mode noise immunity microcontroller interface the following table is the requirement of micorcontroller i/o pin to interface with the w 91030b: case rngon sleep fske dclk data fdrn fcdn intn algo 1 c c c c c c c c c 2 c c c c c c o c c 3 c c h c c c o c c 4 c c h c c o o c c 5 c c h c c c o o c 6 c c h c c o o o c 7 c c h o c o o o c note: "c" is connected with microcontroller, "o" is not connected with microcontroller, "h": this pin must set in high state. inp inn gcfb vref cap rngdi rngon mode osci osco vss rngrc vdd algrc algr algo intn fcdn fdrn data dclk fske sle ep/ reset test +5 v 34 k 430 k 22 nf tip/a +5 v 430 k 22 nf ring/b 34 k 464 k 60 k4 +5 v 150 k 0.22 uf +5 v 200 k 0.01 uf 470 k + - vz 0.1 uf 0.33 uf 12 k +5 v +5 v 0.1 uf r2 r1 +5 v 53 k6 w91030b fsk 3 - wire interface mode 0 selected. resistor must have 1% to lerance. resistor may have 5% tolerance. crystal is 3.579545mhz with 0.1% frequency tolerance. r1, r2 must calculated according to the formula of fig. 7 - 6 (a) for bellcore or bt application. 0.1 uf must reset by microcontroller or by rc p ulse. (this net must as short as
p reliminary w91030b publication release date: march 2000 - 23 - revision a1 case 1: this is the best case for microcontroller to monitor the w91030b, any condition can be monitored. case 2: analog fsk carrier detect output is not very important, fcdn pin can be ignored. case 3: if fske pin is not controlled by microcontroller, this pin must set in high state and the fsk decode circuit is always active when w91030b is not in sleep state. the microcontroller must take care and ignore the false data when the fsk signal is not expected. case 4: the fdrn pin is not very important during fsk decoding if intn pin is used to interrupt the microcontroller. case 5: if the microcontroller has no interrupt pin to use, any signal occurs of ringing, alert or byte bo undary of fsk data can not notify the microcontroller, the microcontroller must always monitoring the rngon, algo or fdrn. case 6: if fdrn pin can not monitored by microcontroller and the microcontroller has no interrupt pin to use. in this case, the mode pin must set low and the w91030b will drive dclk pin. the microcontroller must track the timing of dclk pin, it is a byte boundary if dclk high for at least one bit width (1/1200 sec). case 7: if fdrn pin and dclk pin can not monitored by microcontroller a nd the microcontroller has no interrupt pin to use. in this case, the mode pin must set low to set fsk data interface mode at mode 0 and the microcontroller must track the timing of data pin. the data pin will be toggled with 1/1200 second when fsk channel seizure input and stay in high state when fsk mark signal input, when fsk data input, start bit (low) follows bit 0, bit 1, ... through bit 7 then at least one bit of stop bit (high). the microcontroller must wait for the start bit and synchronize it, acq uire each bit data at proper time and check the stop bit and then wait for next start bit arrival. the timer in the microcontroller must reset at the falling edge of the data pin after stop bit has been detected. application environment there are three ma jor timing differences for caller id sequences, bellcore, bt and cca. figure 9 - 3 is the timing diagram for the bellcore on - hook data transmission and figure 9 - 4 is the timing diagram for the bellcore off - hook data transmission. figure 9 - 5 is the timing dia gram for the bt caller display service on - hook data transmission and figure 9 - 6 is the timing diagram for the bt caller display service off - hook data transmission. figure 9 - 7 is the timing diagram for the cca caller display service for on - hook data transmi ssion.
p reliminar y w91030b - 24 - tip/ring rngon sleep fske fcdn fdrn dclk data 1st ring ch. seizure mark message 2nd ring a note 1 note 2 ... ...101010... b c d e f data ... note 4 note 3 note 5 intn ... ... figure 9 - 3. input and output timing of bellcore on - hook data transmission a = 2 sec typical b = 250 - 500 ms c = 250 ms d = 150 ms e = depends on data length max c + d + e = 2.9 to 3.7 sec f 3 200 ms n otes: 1. the cpe designer may choose to wake up the w91030b only after the end of the rngon signal to conserve power for a battery operated cpe. the delay from rngon to sleep (and fske) is the reactive time of the microcontroller. 2. the cpe designer may choose to set fske to be always high while the cpe is on - hook when the fsk signal is expected. 3. the microcontroller places the w91030b in a sleep condition after the last byte (check sum) has been decoded or fcdn has become inactive. 4. the w91030b may not be woken up at this ring signal after the fsk data has been processed. 5. if the w91030b has been woken up at the 2nd ring, the microcontroller times out if fcdn is not activated and then puts the w91030b into a sleep condition.
p reliminary w91030b publication release date: march 2000 - 25 - revision a1 tip/ring sleep fske fcdn fdrn dclk data note 1 algo cpe unmutes handset and enables keypad g cas note 2 t rec t abs a b ack c cpe goes off-hook d e f mark message note 5 cpe sends cpe mutes handset & disables keypad note 3 ... data note 4 intn ... figure 9 - 4. input and output timing of bellcore off - hook data transmission a = 75 - 85 ms b = 0 - 100 ms c = 55 - 65 ms d = 0 - 500 ms e = 58 - 75 ms f = depends on data length g 50 ms notes: 1. in a cpe where ac power is not available, the design er may choose to switch over to line power when the cpe goes off - hook and use battery power while on - hook. 2. the fske pin may be set low to prevent the alert tone, speech or other fsk inband noise decoded by fsk demodulator and give false data when the dual tone alert signal is expected. if the fske pin can not controlled by microcontroller, the fske pin must always placed in high state and the microcontroller must give up the fsk decoded data when the fsk signal is not expected. 3. fske should be set high as soon as the cpe has finished sending the acknowledge signal ack. 4. fske may be set low after the last byte (check sum) has been decoded or fcdn has become inactive. 5. for unsuccessful attempts where the end office does not send the fsk signal, th e cpe should disable fske, unmute the handset and enable the keypad after this interval has elapsed.
p reliminar y w91030b - 26 - a/b wires rngon sleep algo te dc load te ac load fske fcdn fdrn dclk data line reversal alert signal ch. seizure mark message ring t rec t abs 15 1 ms 20 5 ms a b c d e f g ... ... ...101010... data note 1 50 - 150 ms note 2 note 3 note 4 < 120 ua < 0.5 ma (optional) zss (refer to sin227) current wetting pulse (refer to sin227) intn ... ... a >= 100 ms b = 88 - 110 ms c >= 45 ms (up to 5 sec) d = 80 - 262 ms e = 45 - 75 ms f <= 2.5 sec (500 ms typical) g >= 200 ms figure 9 - 5. input and output timing of bt idle state (on - hook) data transmission notes: 1. sin227 specifies that the ac and dc load s should be applied at 20 5 ms after the end of the dual tone alert signal. 2. sin227 specifies that the ac and dc loads should be removed between 50 - 150 ms after the end of the fsk signal. the w91030b may also be placed in a sleep condition. 3. the fsk e pin should be set low to disable the fsk demodulator when fsk is not expected. the tone alerting signal speech and the dtmf tones are in the same frequency band as the fsk signal. if the fske pin can not controlled by microcontroller, the fske pin must always placed in high state and the microcontroller mu st give up the fsk decoded data when the fsk signal is not expected. 4. the w91030b may not be woken up at this ring signal after the fsk data has been processed.
p reliminary w91030b publication release date: march 2000 - 27 - revision a1 tip/ring sleep fske fcdn fdrn dclk data note 1 algo cpe unmutes handset and enables keypad g alert signal note 2 t rec t abs a b ack c cpe goes off-hook d e f mark message note 6 cpe sends cpe mutes handset & disables keypad note 4 ... data note 5 intn ... start point note 3 h figure 9 - 6. inp ut and output timing of bt loop state (off - hook) data transmission a = 40 - 50 ms b = 80 - 85 ms c = 100 ms d = 65 - 75 ms e = 5 - 100 ms f = 45 - 75 ms g = depends on data length h 100 ms notes: 1. in a cpe where ac power is not available, the designer may choose to switch over to line power when the cpe goes off - hook and use battery power while on - hook. 2. the fske pin may be set low to prevent the alert tone, speech or other fsk inband noise decoded by fsk demodulator and give false data when the dual tone alert signal is expected. if the fske pin can not controlled by microcontroller, the fske pin must always placed in high state and the microcontroller must give up the fsk decoded data when the fsk signal is not expected. 3. the excha nge will have already disabled the speech path to the distant customer in both transmission directions. 4. the fske should be set high as soon as the cpe has finished sending the acknowledge signal ack. 5. the fske may be set low after the last byte (check sum) has been decoded or fcdn has become inactive. 6. in unsuccessful attempts where the exchange does not send the fsk signal, the cpe should disable fske, unmute the handset and enable the keypad after this interval.
p reliminar y w91030b - 28 - a/b wires rngon sleep te dc load te ac load fske fcdn fdrn dclk data line reversal ring burst ch. seizure mark message first ring cycle a b c d e f ... ... ...101010... data note 2 note 3 note 4 intn ... ... a = 200 - 450 ms b >= 500 ms c = 80 - 262 ms d = 45 - 262 ms e <= 2.5 sec (500 ms typical) f >= 200 ms 250 - 400 ms 50 - 150 ms note 1 figure 9 - 7. i nput and output timing of cca caller display service data transmission notes: 1. the cpe designer may choose to set fske always high while the the cpe is on - hook and the fsk signal is expected. 2. tw/p & e/312 specifies that the ac and dc loads should be applied between 250 - 400 ms after the end of the ring burst. 3. tw/p & e/312 specifies that the ac and dc loads should be removed between 50 - 150 ms after the end of the fsk signal. the w91030b may also be placed in a sleep condition. 4. the w91030b may no t be woken up at the first ring cycle after the fsk data had been processed.
p reliminary w91030b publication release date: march 2000 - 29 - revision a1 package dimensions 24l pdip - 600mil seating plane 1.63 1.47 0.064 0.058 symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.060 1.52 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.555 0.550 0.545 14.10 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 1.250 1.260 31.75 32.00 0 15 0.085 2.16 0.650 0.630 16.00 16.51 15 0 e a 2 a c e base plane 1 a 1 e l a s 1 e d 1 b b 24 13 12 1 \ \
p reliminar y w91030b - 30 - package dimensions, continued 24l sop - 300mil l o c e h a1 a e b d seating plane y 0.25 gauge plane e 1 24 13 12 7.60 0.32 0.51 0.30 e c b a1 7.40 0.23 0.33 0.10 0.299 0.013 0.020 0.012 0.291 0.009 0.013 0.004 max. dimension in mm 2.65 a symbol min. 2.35 dimension in inches 0.104 min. 0.093 max. control demensions are in milmeters. 1.27 0.10 10.65 l q y h 0 8 0.40 10.00 e 1.27 bsc 0.050 0.004 0.419 0 0.016 0.394 8 0.050 bsc e d 15.20 15.60 0.598 0.614
p reliminary w91030b publication release date: march 2000 - 31 - revision a1 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792766 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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